Assembly language uses mnemonics to represent machine instructions, providing direct hardware control with one-to-one correspondence to machine code.
Key Benefits: Faster execution, smaller program size, direct hardware access, essential for system programming and embedded systems.
MOV A, B - operand in registerMVI A, 25H - operand in instructionLDA 2000H - operand address given directlyMOV A, M - address in register pair (HL)CMA - operand implied by instructionMOV AX, BX ; AX ← BX
ADD AL, CL ; AL ← AL + CLMOV AL, 25H ; AL ← 25H
MOV BX, 1234H ; BX ← 1234HMOV AX, [1234H] ; AX ← [DS:1234H]
MOV [2000H], BL ; [DS:2000H] ← BLValid registers: BX, SI, DI, BP Default segments: BX/SI/DI→DS, BP→SS
MOV AX, [BX] ; AX ← [DS:BX]
MOV [SI], AL ; [DS:SI] ← AL
MOV [BP], DX ; [SS:BP] ← DXBase registers: BX, BP
MOV AX, [BX+4] ; AX ← [DS:BX+4]
MOV AL, [BP+6] ; AL ← [SS:BP+6]
MOV [BX+100], CX ; [DS:BX+100] ← CXIndex registers: SI, DI
MOV AX, [SI+2] ; AX ← [DS:SI+2]
MOV [DI+10], BL ; [DS:DI+10] ← BLCombinations: BX+SI, BX+DI, BP+SI, BP+DI
MOV AX, [BX+SI] ; AX ← [DS:BX+SI]
MOV [BP+DI], AL ; [SS:BP+DI] ← ALMost complex: Base + Index + Displacement
MOV AL, [BX+SI+5] ; AL ← [DS:BX+SI+5]
MOV [BP+DI+10], CX ; [SS:BP+DI+10] ← CXPhysical Address = Segment Register × 16 + Offset
Example: DS = 2000H, BX = 0150H
Physical Address = 2000H × 16 + 0150H = 20150HMOV AL, ES:[BX] ; Use ES instead of default DS
MOV [SS:DI], CX ; Use SS instead of default DSMOV A, B ; Move register to register
MVI A, 25H ; Move immediate to register
LDA 2000H ; Load accumulator direct
STA 3000H ; Store accumulator direct
LXI H, 2000H ; Load register pair immediate
LDAX B ; Load accumulator indirect
STAX D ; Store accumulator indirect
PUSH H ; Push register pair on stack
POP H ; Pop register pair from stack
XTHL ; Exchange top of stack with HL
SPHL ; Copy HL to SP
PCHL ; Jump to address in HL
XCHG ; Exchange DE and HLADD B ; Add register to A
ADC C ; Add register to A with carry
SUB D ; Subtract register from A
SBB E ; Subtract register from A with borrow
INR A ; Increment register
DCR B ; Decrement register
DAD B ; Add register pair to HL
ADI 25H ; Add immediate to A
ACI 30H ; Add immediate to A with carry
SUI 15H ; Subtract immediate from A
SBI 20H ; Subtract immediate from A with borrowANA B ; AND register with A
ANI 0FH ; AND immediate with A
ORA C ; OR register with A
ORI F0H ; OR immediate with A
XRA D ; XOR register with A
XRI AAH ; XOR immediate with A
CMP E ; Compare register with A
CPI 25H ; Compare immediate with A
CMA ; Complement A
CMC ; Complement carry flagJMP 2000H ; Unconditional jump
JZ 3000H ; Jump if zero
JNZ 3000H ; Jump if not zero
JC 3000H ; Jump if carry
JNC 3000H ; Jump if no carry
JP 3000H ; Jump if positive
JM 3000H ; Jump if minus
JPE 3000H ; Jump if parity even
JPO 3000H ; Jump if parity odd
CALL 5000H ; Call subroutine
CC 5000H ; Call if carry
CNC 5000H ; Call if no carry
CZ 5000H ; Call if zero
CNZ 5000H ; Call if not zero
RET ; Return from subroutine
RC ; Return if carry
RNC ; Return if no carryPUSH PSW ; Push accumulator and flags
POP PSW ; Pop accumulator and flags
EI ; Enable interrupts
DI ; Disable interrupts
HLT ; Halt processor
NOP ; No operation
RST 3 ; Restart (call to specific address)MOV AX, BX ; Move data
PUSH AX ; Push on stack
POP BX ; Pop from stack
XCHG AX, BX ; Exchange
IN AL, 60H ; Input from port
OUT 61H, AL ; Output to port
LEA SI, [BX+4] ; Load effective address
LDS SI, [BX] ; Load pointer using DS
LES DI, [BX] ; Load pointer using ES
LAHF ; Load AH from flags
SAHF ; Store AH to flags
PUSHF ; Push flags
POPF ; Pop flags
XLAT ; Translate byte in ALADD AX, BX ; Addition
ADC CX, DX ; Add with carry
SUB AX, BX ; Subtraction
SBB CX, DX ; Subtract with borrow
MUL BL ; Unsigned multiply
IMUL CL ; Signed multiply
DIV BL ; Unsigned divide
IDIV CL ; Signed divide
INC AX ; Increment
DEC BX ; Decrement
NEG AX ; Two's complement
CMP AX, BX ; Compare
AAA ; ASCII adjust for addition
AAS ; ASCII adjust for subtraction
AAM ; ASCII adjust for multiplication
AAD ; ASCII adjust for divisionAND AX, BX ; Logical AND
OR CX, DX ; Logical OR
XOR AX, BX ; Logical XOR
NOT BX ; One's complement
SHL AL, 1 ; Shift left
SHR BL, CL ; Shift right
SAL DL, 1 ; Arithmetic shift left
SAR DH, CL ; Arithmetic shift right
TEST AL, 01H ; Test bits (AND without storing)MOVSB/MOVSW ; Move string
CMPSB/CMPSW ; Compare string
SCASB/SCASW ; Scan string
LODSB/LODSW ; Load string
STOSB/STOSW ; Store stringJMP LABEL ; Unconditional jump
JE/JZ LABEL ; Jump if equal/zero
JNE/JNZ LABEL ; Jump if not equal/not zero
JA/JNBE LABEL ; Jump if above (unsigned)
JB/JNAE LABEL ; Jump if below (unsigned)
JG/JNLE LABEL ; Jump if greater (signed)
JL/JNGE LABEL ; Jump if less (signed)
CALL PROC ; Call procedure
RET ; Return
LOOP LABEL ; Loop with CX counter
INT 21H ; Software interrupt
IRET ; Interrupt returnIdentical to 8086 - same mnemonics, same opcodes, same functionality. The only differences are:
| Feature | 8085 | 8086 | 8088 |
|---|---|---|---|
| Architecture | 8-bit | 16-bit | 16-bit internal, 8-bit external |
| Data Bus | 8-bit | 16-bit | 8-bit |
| Address Bus | 16-bit | 20-bit | 20-bit |
| Memory Addressing | 64KB | 1MB | 1MB |
| Registers | 7 main registers | 14 main registers | 14 main registers |
| Register Pairs | 3 pairs (BC, DE, HL) | Multiple combinations | Multiple combinations |
| Addressing Modes | 5 modes | 8 modes | 8 modes |
| Instruction Queue | None | 6 bytes | 4 bytes |
| Pipelining | No | Yes (fetch/execute) | Yes (fetch/execute) |
| Instruction Set Size | 78 instructions | 100+ instructions | 100+ instructions |
| Segmentation | No | Yes (4 segments) | Yes (4 segments) |
| Clock Speed | 3 MHz | 5-10 MHz | 5-8 MHz |
| Pins | 40 | 40 | 40 |
| Multiplication/Division | Software only | Hardware MUL/DIV | Hardware MUL/DIV |
| String Operations | No | Yes | Yes |
| Used In | Simple embedded systems | High-end systems | IBM PC (original) |
8085 Version:
LDA 2000H ; Load first number
MOV B, A ; Save in B
LDA 2001H ; Load second number
ADD B ; Add B to A
STA 2002H ; Store result
HLT ; Stop8086/8088 Version:
MOV AL, [2000H] ; Load first number
ADD AL, [2001H] ; Add second number
MOV [2002H], AL ; Store result
HLT ; Stop8085 Version:
LXI H, 2000H ; Point to array
MOV A, M ; Load first element as max
MVI B, 04H ; Counter for remaining elements
LOOP: INX H ; Point to next element
CMP M ; Compare with current element
JNC SKIP ; Jump if A >= M
MOV A, M ; Update maximum
SKIP: DCR B ; Decrement counter
JNZ LOOP ; Continue if not zero
STA 2005H ; Store maximum
HLT8086/8088 Version:
LEA SI, ARRAY ; Point to array
MOV AL, [SI] ; Load first element
MOV CX, 4 ; Counter for remaining elements
INC SI ; Point to next element
AGAIN:
CMP AL, [SI] ; Compare with current element
JGE SKIP ; Jump if AL >= [SI]
MOV AL, [SI] ; Update maximum
SKIP:
INC SI ; Point to next element
LOOP AGAIN ; Continue loop
MOV MAX, AL ; Store result
HLTThis focused guide emphasizes the critical concepts you need to master, especially the detailed addressing modes and comprehensive comparison of all three processors. The addressing modes section is particularly important as it forms the foundation for effective assembly programming in 8086/8088 systems.